The present disclosure relates to a semiconductor memory device, and more particularly, to failure diagnosis of an address decoder.
Information processors include microcontrollers, microprocessors, signal processors, image processors, voice processors and the like. A memory circuit is incorporated in the microcontroller which is an example of the information processors. The memory circuit includes a memory part to store data, and an address decoder in which an input signal of n bits is input to assert one signal of 2n selected signals to select data stored in the memory part. The integration of a failure detection function into the memory circuit is becoming increasingly popular to improve safety and relatability of equipment including memory circuits such as the microcontroller described above.
ISO26262 (international functional safety standard for electric and electronic automotive systems) requires failure detection during operation of an address decoder of a static random access memory (SRAM).
For example, general techniques such as error-correcting code (ECC) and parity are used as the failure detection function of the memory part which is the data storage part of the memory circuit (see, for example, Patent Document 1 (Japanese Patent Application Laid-Open No. 2007-257791)).
However, the technique such as ECC or parity enables failure detection based on the data actually read from the memory part, so that if a failure is detected with this technique, it is difficult to determine whether the cause of the failure is in the memory part or in the address decoder. Thus, failure detection of the address decoder is required in the memory circuit in addition to failure detection of the memory part. In other words, not only determining whether the address is correctly decoded, but also determining whether another address is not selected is required.
From this point of view, Japanese Patent Application Laid-Open No. 2010-86120 (Patent Document 2) describes a technique for performing failure detection of the address decoder by generating an error detection signal from the address and data, writing the error detection signal in the memory together with the data, and when the data is read, comparing the error detection bit generated from the read address with the read error detection bit.
Further, Japanese Patent Application Laid-Open No. 2010-73285 (Patent Document 3) describes a technique for performing failure detection of the address decoder by inverting at least one bit of the input signal of the address decoder in the SRAM macro, and comparing with logic values of a predetermined bit signal pair.